Ultra Low-Power Fault-Tolerant SRAM Design in 90nm CMOS Technology
نویسنده
چکیده
.................................................................................................................................. iii TABLE OF CONTENTS ............................................................................................................... iv LIST OF FIGURES ....................................................................................................................... vi LIST OF TABLES ......................................................................................................................... ix LIST OF ABBREVIATIONS ......................................................................................................... x CHAPTER 1 BACKGROUND AND MOTIVATION .............................................................. 1 1.1 Ultra Low-Power Design ..................................................................................................... 1 1.2 Single Event Upset Tolerant Design .................................................................................... 3 1.3 Thesis Outline ...................................................................................................................... 4 CHAPTER 2 INTRODUCTION ................................................................................................ 5 2.1 Conventional SRAM Cell and SNM.................................................................................... 5 2.2 Challenges for Sub-Threshold SRAM Design ..................................................................... 8 2.2.1 Stability of SRAM Cells .................................................................................................... 8 2.2.2 Sense Amplifier Problems ................................................................................................. 9 2.2.3 Reduced Number of Cells Per Bitline ................................................................................ 9 2.3 Previous Sub-Threshold SRAM Design ............................................................................ 11 2.3.1 Verma’s 8T Sub-Threshold SRAM ................................................................................. 11 2.3.2 Kim’s 10T Sub-Threshold SRAM ................................................................................... 13 2.3.3 Jinhui Chen’s Sub-Threshold Register File Design ......................................................... 15 2.3.4 Zhai’s 6T Sub-Threshold SRAM design ......................................................................... 16 2.3.5 Chang’s 10T Sub-Threshold SRAM Design ................................................................... 17 2.3.6 Sub-Threshold SRAM Design Summary......................................................................... 18 2.4 Single-Event Upset in SRAM Design and Mitigation Methods ........................................ 18 CHAPTER 3 FAULT TOLERANT ULTRA LOW-POWER SRAM DESIGN...................... 23 v 3.1 Overview of the Chip Design ............................................................................................ 23 3.2 Detailed SRAM Design ..................................................................................................... 25 3.2.1 Fault Tolerant Sub-Threshold SRAM Cell Design .......................................................... 25 3.2.2 Replica Technique for Read Operation Employing Dummy Column and Row ............. 28 3.2.3 Sense Amplifier Design ................................................................................................... 31 3.2.4 Boost Circuit Design ........................................................................................................ 33 3.2.5 Row and Column Decoders ............................................................................................. 34 3.2.6 Address Transition Detector (ATD) ................................................................................ 35 3.2.7 Input / Output Buffer Design ........................................................................................... 37 3.3 Read and Write Control Sequences ................................................................................... 38 3.3.1 Read Control Sequence .................................................................................................... 38 3.3.2 Write Control Sequence ................................................................................................... 40 3.4 Layout of the SRAM Design ............................................................................................. 42 CHAPTER 4 DESIGN SIMULATION AND VERIFICATION .............................................. 44 4.1 Verification of Critical Components in SRAM Chip ........................................................ 44 4.1.1 SRAM Cell Simulation .................................................................................................... 45 4.1.2 Sense Ampplifer Simulation ............................................................................................ 46 4.1.3 Verification of Voltage Boosting Circuit ......................................................................... 47 4.1.4 Verification of ATD Circuit............................................................................................. 48 4.2 Verification for the Overall SRAM Chip........................................................................... 49 4.3 Performance Simulation of the SRAM Design .................................................................. 54 CHAPTER 5 CHIP TESTING RESULTS ................................................................................ 56 5.1 SRAM Functional Testing ................................................................................................. 56 5.1.1 Testing Board Configuration ........................................................................................... 56 5.1.2 Functional Testing Results ............................................................................................... 59 5.2 Single Event Upset Tolerance Testing ............................................................................... 62 5.3 Testing Results Analysis .................................................................................................... 63 CHAPTER 6 CONCLUSION AND FUTURE WORK ........................................................... 65 6.1 Summary and Conclusions ................................................................................................ 65 6.2 Future Work ....................................................................................................................... 66
منابع مشابه
Deep Sub-Micron SRAM Design for Ultra-Low Leakage Standby Operation
Deep Sub-Micron SRAM Design for Ultra-Low Leakage Standby Operation by Huifang Qin Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Jan M. Rabaey, Chair Suppressing the standby current in memories is critical in low-power design. By lowering the supply voltage (VDD) to its standby limit, the data retention voltage (DRV...
متن کاملAnalysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology
Limited energy consumption in multimedia requires very low power circuits. In this paper we focused on leakage current minimization in single static random access memory (SRAM) cell in 90nm complementary metal oxide semiconductor (CMOS) technology. The leakage current mainly consists of sub threshold leakage current and gate leakage current in 90nm CMOS technology. So minimizing the sub thresho...
متن کاملDesign and Implementation of Low Leakage SRAM Acrhitectures using CMOS VLSI Circuits in Different Technology Environment
There is a demand for portable devices like mobiles and laptops etc. and their long battery life. For high integrity CMOS VLSI circuit design in deep submicron regime, feature size is reduced according to the improved technology. Reduced feature size devices need low power for their operation. Reduced power supply, reduces the threshold voltage of the device. Low threshold devices have improved...
متن کاملA 0.3V 1kb Sub-Threshold SRAM for Ultra-Low- Power Application in 90nm CMOS
Ultra-low power device is very popular in recent years because of some applications like medical device and communications. For the ultralow-power consideration, the crucial in SRAMs are stability and reliability. In conventional 6T SRAMs is hard to achieve reliability in sub-threshold operation. Hence, some researchers have considered different configuration SRAMs cell for sub-threshold operat...
متن کاملA Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power SRAM
A novel ultra high speed, compact and least sensitive to process variation, hybrid sense amplifier is designed for ultra low power SRAM. Precisely sized current mode circuit (CMC) is designed to provide differential current from bit-lines. We eliminate the global sensing stage to save silicon area and sized the output buffers to achieve full logic swing at the output of proposed sense amplifier...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2010